Is Hedonic Regression a Viable Damages Framework? The Federal Circuit Leaves this Question Open in VLSI Technology LLC v. Intel
January 30, 2024
By Andrew N. Schneider; Alissa E. Green; Gracie K. Mills; J. Preston (J.P.) Long, Ph.D.
When calculating patent damages, parties often face the task of apportioning value between patented and unpatented features. Although one can approach this task in various ways, the increased use of hedonic regression has emerged as one of the most notable trends in recent years, especially in litigation involving high-tech inventions.[1] Put succinctly, hedonic regression attempts to identify the constituent characteristics of an allegedly infringing device or process, then to estimate how much each characteristic, especially the allegedly inventive characteristics, contributes to the overall value of the device or process.
In VLSI Technology LLC v. Intel Corporation,[2] the Federal Circuit addressed hedonic regression for the first time. Although the court ultimately vacated the district court’s $1.5 billion damages award, it left the viability of the hedonic regression methodology itself as an open question.
At trial, Intel presented a damages theory based on comparable licenses—something the Federal Circuit previously remarked “may be the most effective method of estimating the asserted patent’s value.”[3] VLSI declined to adopt such an approach, opting instead to employ a more novel, four-step hedonic regression analysis:
The district court jury awarded $1.5 billion in damages to VLSI.
On appeal, the Federal Circuit vacated the jury’s award because the hedonic regression analysis hinged on “a readily identifiable error” that “departed from the essential logic of the value-of-the-patented-technology assessment.”[4] Specifically, the estimated power savings (step 1 above) derived from processor configurations that Intel’s products did not use.[5] Because VLSI’s error improperly inflated the damages award, the panel remanded the case to the district court for a new damages trial.
As for whether VLSI’s hedonic regression analysis constitutes a viable damages methodology more generally, the panel noted only that “Intel, in this court, has not persuasively shown that the regression analysis used to determine price effects of speed improvements is an improper or unreasonable one.”[6] On remand, Intel may have the opportunity to better explain its challenges to VLSI’s hedonic regression analysis.
Although VLSI was the first time the Federal Circuit addressed hedonic regression analysis, Judge Dyk—one of the three Federal Circuit panelists in VLSI—previously had an opportunity to consider similar issues while sitting by designation in the Eastern District of Texas. In Stragent, LLC v. Intel Corp., Judge Dyk identified faulty assumptions in the plaintiff’s hedonic regression analysis and expressed doubt as to whether it is a viable damages methodology at all.[7] Striking opinions offered by Stragent’s damages expert, he remarked that “[e]ven assuming that hedonic regression analysis could properly be used to calculate the value of the accused feature, I conclude that [the expert]’s methodology relies on arbitrary assumptions that have no basis in the facts of this case or hedonic analysis in general.”[8] The expert had assigned equal value to 19 different features, and his “own description of hedonic regression analysis suggests that such subjective assessments are not reliable indicators of consumer marketplace behavior.”[9]
VLSI’s hedonic regression analysis may have been more detailed than Stragent’s, but it, too, hinged on improper assumptions not adequately grounded in the facts of the case.[10] The question following VLSI remains whether such difficulties will render hedonic regression too untethered from the case in practice—much like the 25% rule of thumb[11] and Nash bargaining solution[12] before it—or whether hedonic regression models will survive further scrutiny as they continue to gain popularity among patent owners.
[1] See generally J.P. Long, “Apportionment in the Semiconductor Age,” IP Litigator at 1-9 (Mar./Apr. 2021), available at https://www.finnegan.com/a/web/7Zpw8fRtQUB7ADW5mnNZTr/published-ip-litigator-apportionment-in-the-semiconductor-age-jpl-march-april-2021.pdf.
[2] 87 F.4th 1332 (Fed. Cir. 2023), slip op. available at https://cafc.uscourts.gov/opinions-orders/22-1906.OPINION.12-4-2023_2231550.pdf.
[3] CSIRO v. Cisco Sys., 809 F.3d 1295, 1303-04 (Fed. Cir. 2015).
[4] See VLSI Tech. LLC v. Intel Corp., 87 F.4th 1332, 1347 (Fed. Cir. 2023).
[5] See id. at 1347-48.
[6] Id. at 1349.
[7] See No. 6:11-CV-421, 2014 WL 1389304, at *3-4 (E.D. Tex. Mar. 6, 2014) (Dyk, J., sitting by designation).
[8] Id. at *4.
[9] Id. at *4.
[10] As another example, consider KAIST IP US LLC v. Samsung Electronics Co. The trial court initially permitted expert opinions based on a hedonic regression analysis, then granted a post-trial motion for remittitur or a new trial after the jury returned a $200 million verdict. See 439 F. Supp. 3d 860, 890-91 (E.D. Tex. 2020).
[11] See Uniloc USA, Inc. v. Microsoft Corp., 632 F.3d 1292, 1314-18 (Fed. Cir. 2011) (“In this case, it is clear that [the expert]’s testimony was based on the use of the 25% rule of thumb as an arbitrary, general rule, unrelated to the facts of this case.”).
[12] See VirnetX, Inc. v. Cisco Sys., Inc., 767 F.3d 1308, 1331-34 (Fed. Cir. 2014) (“Anyone seeking to invoke the [Nash bargaining solution] as applicable to a particular situation must establish that fit, because the 50/50 profit-split result is proven by the theorem only on those premises.”).
Copyright © Finnegan, Henderson, Farabow, Garrett & Dunner, LLP. This article is for informational purposes, is not intended to constitute legal advice, and may be considered advertising under applicable state laws. This article is only the opinion of the authors and is not attributable to Finnegan, Henderson, Farabow, Garrett & Dunner, LLP, or the firm’s clients.
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